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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1999 oct 05 integrated circuits TSA5059 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer
1999 oct 05 2 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 features complete 2.7 ghz single chip system optimized for low phase noise selectable divide-by-two prescaler operation up to 2.7 ghz with and without divide-by-two prescaler selectable reference divider ratio compatible with uk-dtt (digital terrestrial television) offset requirements selectable crystal/comparison frequency output four selectable charge pump currents four selectable i 2 c-bus addresses standard and fast mode i 2 c-bus i 2 c-bus compatible with 3.3 and 5 v microcontrollers 5-level analog-to-digital converter (adc) low power consumption 33 v tuning voltage drive three i/o ports and one output port. applications sat, tv, vcr and cable tuning systems digital set-top boxes. general description the TSA5059 is a single chip pll frequency synthesizer designed for satellite and terrestrial tuning systems up to 2.7 ghz. the rf preamplifier drives the 17-bit main divider enabling a step size equal to the comparison frequency, for an input frequency up to 2.7 ghz. a fixed divide-by-two additional prescaler can be inserted between the preamplifier and the main divider to give a software compatibility with existing ics. in this case, the step size is twice the comparison frequency. the comparison frequency is obtained from an on-chip crystal oscillator that can also be driven from an external source. either the crystal frequency or the comparison frequency can be switched to the xt/comp output pin to drive the reference input of another synthesizer or the clock input of a digital demodulation ic. both divided and comparison frequency are compared into the fast phase detector which drives the charge pump. the loop amplifier is also on-chip, including the high-voltage transistor to drive directly the 33 v tuning voltage, without the need of an external transistor. control data is entered via the i 2 c-bus; five serial bytes are required to address the device, select the main divider ratio, the reference divider ratio, program the four output ports, set the charge pump current, select the prescaler by two, select the signal to switch to the xt/comp output pin and/or select a specific test mode. three of the four output ports can also be used as input ports and a 5-level adc is provided. digital information concerning the input ports and the adc can be read out of the TSA5059 on the sda line (one status byte) during a read operation. a flag is set when the loop is in-lock and is read during a read operation, as well as the power-on reset flag. the device has four programmable addresses, programmed by applying a specific voltage at pin as, enabling the use of multiple synthesizers in the same system.
1999 oct 05 3 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 quick reference data v cc = 4.5 to 5.5 v; t amb = - 20 to +85 c; unless otherwise speci?ed. note 1. asymmetrical drive on pin rfa or rfb; see fig.3. ordering information symbol parameter conditions min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v i cc supply current t amb =25 c 303745ma f i(rf) rf input frequency 64 - 2700 mhz v i(rf)(rms) rf input voltage (rms value) f i(rf) from 64 to 150 mhz; note 1 12.6 - 300 mv - 25 - +2.5 dbm f i(rf) from 150 to 2200 mhz; note 1 7.1 - 300 mv - 30 - +2.5 dbm f i(rf) from 2.2 to 2.7 ghz; note 1 22.4 - 300 mv - 20 - +2.5 dbm f xtal crystal frequency 4 - 16 mhz t amb ambient temperature - 20 - +85 c t stg storage temperature - 40 - +150 c type number package name description version TSA5059t so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 TSA5059ts ssop16 plastic shrink small outline package; 16 leads; body width 4.4 mm sot369-1
1999 oct 05 4 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 block diagram fig.1 block diagram. handbook, full pagewidth fce120 pre amp 33 v amp lock detect digital phase comparator charge pump reference divider divider 1/2 17-bit divider 17-bit latch divide ratio i 2 c-bus transceiver 1-bit latch 2-bit latch 3-bit adc power-on reset mode control logic 3-bit input ports 4-bit latch and output ports xtal oscillator 4-bit latch 2 xtal 13 rfa 14 rfb 4 as 6 scl 5 sda 11 10 9 8 7 adc cp 1 xt/comp 3 vt 16 v cc 12 gnd 15 TSA5059 p3 p2 p1 p0
1999 oct 05 5 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 pinning symbol pin description cp 1 charge pump output xtal 2 crystal oscillator input xt/comp 3 f xtal or f comp signal output as 4 i 2 c-bus address selection input sda 5 i 2 c-bus serial data input/output scl 6 i 2 c-bus serial clock input p3 7 general purpose output port 3 p2 8 general purpose input/output port 2 p1 9 general purpose input/output port 1 p0 10 general purpose input/output port 0 adc 11 analog-to-digital converter input v cc 12 supply voltage rfa 13 rf signal input a rfb 14 rf signal input b gnd 15 ground supply vt 16 tuning voltage output fig.2 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 cp xtal xt/comp as sda gnd rfb rfa v cc adc p0 p1 scl p3 p2 vt TSA5059 fce121 functional description the TSA5059 contains all the necessary elements but a reference source and a loop filter to control a varicap tuned local oscillator forming a phase locked loop frequency synthesized source. the ic is designed in a high speed process with a fast phase detector to allow a high comparison frequency to reach a low phase noise level on the oscillator. the block diagram is shown in fig.1. the rf signal is applied at pins rfa and rfb. thanks to the input preamplifier a good sensitivity is provided. the output of the preamplifier is fed to the 17-bit programmable divider either through a divide-by-two prescaler or directly. because of the internal high speed process, the rf divider is working for a frequency up to 2.7 ghz, without the need for the divide-by-two prescaler to be used. this prescaler is present on chip for compatibility reasons with existing circuits. the output of the 17-bit programmable divider f div is fed into the phase comparator, where it is compared in both phase and frequency with the comparison frequency f comp . this frequency is derived from the signal present at pin xtal, f xtal , divided down in the reference divider. it is possible either to connect a quartz crystal to pin xtal and then using the on-chip crystal oscillator, or to feed this pin with a reference signal from an external source. the reference divider can have a dividing ratio selected from 16 different values between 2 and 320, including the ratio 24 to cope with the offset requirement of the uk-dtt system, see table 8. the output of the phase comparator drives the charge pump and the loop amplifier section. this amplifier has an on-chip high voltage drive transistor which avoids the use of an additional external component. pin cp is the output of the charge pump, and pin vt is the pin to drive the tuning voltage to the varicap diode of the voltage controlled oscillator (vco). the loop filter has to be connected between pins cp and vt. in addition, it is possible to drive another pll synthesizer, or the clock input of a digital demodulation ic, from the pin xt/comp. it is possible to select by software either f xtal , the crystal oscillator frequency or f comp , the frequency present after the reference divider at this pin. it is also possible to switch off this output, in case it is not used. for test and alignment purposes, it is possible to release the tuning voltage output to be able to apply an external voltage on it, to select one of the three charge pump test modes, and to monitor half the f div at port p0. see table 10 for all possible modes.
1999 oct 05 6 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 four open-collector output ports are provided on the ic for general purpose; three of these can also be used as input ports. a 3-bit adc is also available. the TSA5059 is controlled via the two-wire i 2 c-bus. for programming, there is one 7-bit module address and the r/ w bit for selecting read or write mode. to be able to have more than one synthesizer in an i 2 c-bus system, one of four possible addresses is selected depending on the voltage applied at pin as (see table 3). the TSA5059 fulfils the fast mode i 2 c-bus, according to the philips i 2 c-bus specification. the i 2 c-bus interface is designed in such a way that pins scl and sda can be connected either to 5 or to 3.3 v pulled-up i 2 c-bus lines, allowing the pll synthesizer to be connected directly to the bus lines of a 3.3 v microcontroller. write mode: r/ w=0 after the address transmission (first byte), data bytes can be sent to the device (see table 1). four data bytes are needed to fully program the TSA5059. the bus transceiver has an auto-increment facility that permits programming of the TSA5059 within one single transmission (address + 4 data bytes). the TSA5059 can also be partly programmed on the condition that the first data byte following the address is byte 2 or byte 4. the meaning of the bits in the data bytes is given in table 1. the first bit of the first data byte transmitted indicates whether byte 2 (first bit is logic 0) or byte 4 (first bit is logic 1) will follow. until an i 2 c-bus stop condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. to allow a smooth frequency sweep for fine tuning, and while the data of the dividing ratio of the main divider is in data bytes 2, 3 and 4, it is necessary for changing the frequency to send the data bytes 2 to 5 in a repeated sending, or to finish an incomplete transmission by a stop condition. repeated sending of data bytes 2 and 3 without ending the transmission does not change the dividing ratio. to illustrate, the following data sequences will change the dividing ratio: bytes 2, 3, 4 and 5 bytes 4, 5, 2 and 3 bytes 2, 3, 4 and stop bytes 4, 5, 2 and stop bytes 2, 3 and stop bytes 2 and stop bytes 4 and stop. table 1 write data format note 1. msb is transmitted first. byte description msb (1) lsb control bit 1 address 1 1 0 0 0 ma1 ma0 0 a 2 programmable divider 0 n14 n13 n12 n11 n10 n9 n8 a 3 programmable divider n7 n6 n5 n4 n3 n2 n1 n0 a 4 control data 1 n16 n15 pe r3 r2 r1 r0 a 5 control data c1 c0 xce xcs p3 p2/t2 p1/t1 p0/t0 a
1999 oct 05 7 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 table 2 explanation of table 1 address selection (see table 3) the module address contains programmable address bits (ma1 and ma0), which offer the possibility of having up to 4 synthesizers in one system. the relationship between ma1 and ma0 and the input voltage at pin as is given in table 3. table 3 address selection note 1. this address is selected by connecting a 15 k w resistor between pin as and pin v cc . status at power-on reset (por) at power-on or when the supply voltage drops below approximately 2.75 v, internal registers are set according to table 4. table 4 status at power-on reset; note 1 notes 1. x = dont care. 2. at power-on reset, all output ports are in high-impedance state. bit description ma1 and ma0 programmable address bits; see table 3 a acknowledge bit n16 to n0 programmable main divider ratio control bits; n = n16 2 16 + n15 2 15 + ... + n1 2 1 +n0 pe prescaler enable (prescaler by 2 is active when bit pe = 1) r3 to r0 programmable reference divider ratio control bits; see table 8 c1 and c0 charge pump current select bits; see table 9 xce xt/comp enable; xt/comp output active when bit xce = 1; see table 10 xcs xt/comp select; signal select when bit xce = 1, test mode enable when bit xce = 0; see table 10 t2, t1 and t0 test mode select when bit xce = 0 and bit xcs = 1; see table 10 p3, p2 and p1 port p3, p2 and p1 output states p0 port p0 output state, except in test mode; see table 10 ma1 ma0 voltage applied to pin as 0 0 0 to 0.1v cc 0 1 open-circuit 1 0 0.4v cc to 0.6v cc ; note 1 1 1 0.9v cc to v cc byte description msb lsb control bit 1 address 11000ma1ma00 a 2 programmable divider 0 xxxxxxx a 3 programmable divider xxxxxxxx a 4 control data 1 xxxxxxx a 5 control data 0001x (2) 1 (2) x (2) x (2) a
1999 oct 05 8 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 read mode: r/ w=1 data can be read out of the TSA5059 by setting the bit r/ w to logic 1 (see table 5). after the slave address has been recognized, the TSA5059 generates an acknowledge pulse and the first data byte (status word) is transferred on the sda line (msb first). data is valid on the sda line during a high-level of the scl clock signal. a second data byte can be read out of the TSA5059 if the controller generates an acknowledge on the sda line. end of transmission will occur if no acknowledge from the controller occurs.the TSA5059 will then release the data line to allow the controller to generate a stop condition. when ports p0 to p2 are used as inputs, they must be programmed in their high-impedance state. the por flag is set to logic 1 when v cc drops below approximately 2.75 v and at power-on. it is reset to logic 0 when an end of data is detected by the TSA5059 (end of a read sequence). control of the loop is made possible with the in-lock flag which indicates (bit fl = 1) when the loop is phase-locked. the bits i2, i1 and i0 represent the status of the i/o ports p2, p1 and p0 respectively. a logic 0 indicates a low-level and a logic 1 indicates a high-level. a built-in 5-level adc is available at pin adc. this converter can be used to feed afc information to the microcontroller through the i 2 c-bus. the relationship between bits a2, a1, a0 and the input voltage at pin adc is given in table 7. table 5 read data format note 1. msb is transmitted first. table 6 explanation of table 5 table 7 adc levels note 1. accuracy is 0.03v cc . byte description msb (1) lsb control bit 1 address 1 1000ma1ma01 a 2 status byte por fl i2 i1 i0 a2 a1 a0 - bit description a acknowledge bit ma1 and ma0 programmable address bits; see table 3 por power-on reset ?ag (bit por = 1 on power-on) fl in-lock ?ag (bit fl = 1 when the loop is phase-locked) i2, i1 and i0 digital information for i/o ports p2, p1 and p0 respectively a2, a1 and a0 digital outputs of the 5-level adc; see table 7 a2 a1 a0 voltage applied to pin adc (1) 1 0 0 0.6v cc to v cc 0 1 1 0.45v cc to 0.6v cc 0 1 0 0.3v cc to 0.45v cc 0 0 1 0.15v cc to 0.3v cc 0 0 0 0 to 0.15v cc
1999 oct 05 9 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 reference divider ratio the reference divider ratio is set by 4 bits in the write mode, giving 16 different ratios which allow to adjust the comparison frequency to different values, depending on the compromise which has to be found between step size and phase noise. table 8 shows the different dividing ratios and the corresponding comparison frequencies and step size, assuming the device is provided with a 4 mhz signal at pin xtal. the dividing ratio of 24 is implemented to fulfil the uk-dtt recommendation regarding offset frequency of 1 6 mhz. table 8 reference dividing ratios note 1. only valid when the ic is used with a 4 mhz crystal. charge pump current the charge pump current can be chosen from 4 different values depending on the value of bits c1 and c0 in the i 2 c-bus byte 4, according to table 9. table 9 charge pump current r3 r2 r1 r0 ratio comparison frequency (1) step bit pe = 0 (1) bit pe = 1 (1) 0000 2 2mhz 2mhz 4mhz 0001 4 1mhz 1mhz 2mhz 0010 8 500khz 500khz 1mhz 001116 250khz 250khz 500khz 010032 125khz 125khz 250khz 010164 62.5 khz 62.5 khz 125 khz 0110128 31.25 khz 31.25 khz 62.5 khz 0111256 15.625 khz 15.625 khz 31.25 khz 100024 166.67 khz 166.67 khz 333.33 khz 1001 5 800khz 800khz 1.6mhz 101010 400khz 400khz 800khz 101120 200khz 200khz 400khz 110040 100khz 100khz 200khz 110180 50khz 50khz 100khz 1110160 25khz 25khz 50khz 1111320 12.5 khz 12.5 khz 25 khz c1 c0 i cp ( m a) (absolute value) min. typ. max. 0 0 100 135 170 0 1 210 280 350 1 0 450 600 750 1 1 920 1230 1560
1999 oct 05 10 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 xt/comp frequency output it is possible to output either the crystal or the comparison frequency at this pin to be used in the application, for example to drive a second pll synthesizer, saving a quartz crystal in the bill of material. to output f xtal , it is necessary to set bit xce to logic 1 and bit xcs to logic 0, or bit xce to logic 0 and bit xcs to logic 1 during a test mode, while to output f comp , it is necessary to set both bits xce and xcs to logic 1. if the output signal at this pin is not used, it is recommended to disable it, setting both bits xce and xcs to logic 0. table 10 shows how this pin is programmed. at power-on, the xt/comp output is set, with the f xtal signal selected. prescaler enable even if the TSA5059 is able to work with the relation f comp = step size for an input frequency up to 2.7 ghz, this ic is designed to be backward compatible with existing ics for which this relation is only valid for an rf frequency up to 2.0 ghz and in which it is necessary to select a fixed divide-by-two prescaler for frequencies between 2.0 and 2.7 ghz. the prescaler is selected by setting bit pe to logic 1 and it is not in use if bit pe is set to logic 0. for new designs, and especially if it is important to reach a low phase noise on the controlled vco, it is recommended to set bit pe to logic 0, and not to use the prescaler, allowing the comparison frequency to be equal to the step size, whatever the rf frequency is between 64 and 2700 mhz. test modes it is possible to access the test modes setting bit xce to logic 0 and bit xcs to logic 1. one specific test mode is then selected using bits t2, t1 and t0, as described in table 10. table 10 xt/comp and test mode selection; note 1 notes 1. x = dont care. 2. status at power-on reset. xce xcs t2 t1 t0 xt/comp output test mode 0 0 x x x disabled normal operation 1 0xxxf xtal normal operation 1 1xxxf comp normal operation 01000f xtal test operation: charge pump sink; status byte: bit fl = 1 01001f xtal test operation: charge pump source; status byte: bit fl = 0 01010f xtal test operation: charge pump disabled; status byte: bit fl = 0 01011f xtal test operation: 1 2 f div switched to port p0 011xxf xtal test operation: tuning voltage (pin vt) is off (high-impedance); note 2
1999 oct 05 11 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 limiting values in accordance with the absolute maximum rating system (iec 134); note 1. note 1. maximum ratings cannot be exceeded, not even momentarily without causing irreversible ic damage. maximum ratings cannot be accumulated. handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage - 0.3 +6.0 v v (n) voltage on pins cp, xtal, xt/comp, as, p0, p1, p2, p3, adc, rfa and rfb - 0.3 v cc + 0.3 v scl and sda - 0.3 +6.0 v vt - 0.3 +35 v i o(sda) serial data output current - 1.0 +10.0 ma i o(px) p0, p1, p2 and p3 output current port switched on - 1.0 +20.0 ma i o( s px) sum of currents in p0, p1, p2 and p3 - 50.0 ma t amb ambient temperature - 20 +85 c t stg storage temperature - 40 +150 c t j(max) maximum junction temperature - 150 c t sc short-circuit time each pin to v cc or gnd - 10 s symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air TSA5059t (sot109-1; so16) 115 k/w TSA5059ts (sot369-1; ssop16) 144 k/w
1999 oct 05 12 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 characteristics v cc = 4.5 to 5.5 v; t amb = - 20 to +85 c; f xtal = 4 mhz; measured according to fig.4; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply (pin v cc ) v cc supply voltage 4.5 5.0 5.5 v i cc supply current t amb =25 c303745ma v cc(por) supply voltage below which por is active t amb =25 c - 2.75 - v rf inputs (pins rfa and rfb) f i(rf) rf input frequency 64 - 2700 mhz v i(rf)(rms) rf input voltage (rms value) f i(rf) between 64 and 150 mhz; note 1 12.6 - 300 mv - 25 - +2.5 dbm f i(rf) between 150 and 2200 mhz; note 1 7.1 - 300 mv - 30 - +2.5 dbm f i(rf) between 2.2 and 2.7 ghz; note 1 22.4 - 300 mv - 20 - +2.5 dbm z i(rf) rf input impedance see fig.7 --- w c i(rf) rf input capacitance see fig.7 --- pf mdr main divider ratio prescaler disabled 64 - 131071 prescaler enabled 128 - 262142 crystal oscillator (pin xtal) f xtal crystal frequency 4 - 16 mhz ? z xtal ? crystal oscillator negative impedance 4 mhz crystal 400 680 -w z xtal recommended crystal series resistance 4 mhz crystal -- 200 w p xtal crystal drive level 4 mhz crystal; note 2 - 40 -m w f i(ext) external reference input frequency note 3 2 - 20 mhz v i(ext)(p-p) external reference input voltage (peak-to-peak value) note 3 200 - 500 mv phase comparator and charge pump f comp comparison frequency -- 2 mhz n comp equivalent phase noise at the phase detector input f comp = 250 khz; c1=c0=1; in the loop bandwidth -- 157 - dbc/hz ? i cp ? charge pump current c1 = 0; c0 = 0 100 135 170 m a c1 = 0; c0 = 1 210 280 350 m a c1 = 1; c0 = 0 450 600 750 m a c1 = 1; c0 = 1 920 1230 1540 m a i cpl charge pump leakage current - 10 0 +10 na
1999 oct 05 13 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 notes 1. asymmetrical drive on pin rfa or rfb; see fig.3. 2. the drive level is expected with the crystal at series resonance with a series resistance of 50 w . the value will be different with another crystal. 3. to drive pin xtal from the pin xt/comp of another TSA5059, couple the signal through a capacitor of 1 nf (to remove the dc level), in series with an 1.2 k w resistor, see fig.5. tuning voltage output (pin vt) i lo(off) leakage current when switched off xce = 0; xcs = 1; t2 = 1; v vt =33v --- 10 m a v o output voltage when the loop is locked; normal mode; v vt = 33 v; pull-up resistor of 27 k w 0.25 - 32.7 v xt/comp output (pin xt/comp) v o(p-p) ac output voltage (peak-to-peak value) xce = 1 - 400 - mv input/output and output ports (pins p0, p1, p2 and p3) i lo port leakage current port off; v o =v cc -- 10 m a v o(sat) output port saturation voltage port on; i sink =10ma - 0.2 0.4 v v il low-level input voltage -- 1.5 v v ih high-level input voltage 3.0 -- v adc input (pin adc) i lih high-level input leakage current v adc =v cc -- 10 m a i lil low-level input leakage current v adc =0v - 10 -- m a address selection (pin as) i lih high-level input leakage current v as =v cc -- 1ma i lil low-level input leakage current v as =0v - 0.5 -- ma scl and sda inputs (pins scl and sda) v il low-level input voltage -- 1.5 v v ih high-level input voltage 2.3 -- v i lih high-level input leakage current v ih = 5.5 v v cc = 5.5 v -- 10 m a v cc =0v -- 10 m a i lil low-level input leakage current v il =0v; v cc = 5.5 v - 10 -- m a f scl scl clock frequency -- 400 khz sda output (pin sda) v o(ack) output voltage during acknowledge i sink =3ma -- 0.4 v i sink =6ma -- 0.6 v symbol parameter conditions min. typ. max. unit
1999 oct 05 14 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 fig.3 sensitivity curve. handbook, full pagewidth - 18 - 24 - 6 - 12 0 + 6 - 30 - 36 - 42 - 48 - 54 - 60 500 1000 1500 2000 2500 3000 0 guaranteed area v i(rf) (dbm) f (mhz) fce416
1999 oct 05 15 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 application information an example of a typical application is given in fig.4. in this application the vco centre frequency is 1.5 ghz, with a slope of 100 mhz/v; the expected loop bandwidth is 10 khz with a charge pump current of 555 m a and f comp of 250 khz. filter components need to be adapted to each application depending on the vco characteristics and the required performance of the loop. fig.4 typical application. handbook, full pagewidth TSA5059 fce123 1 vt gnd rfb rfa v cc 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 as xt/comp xtal cp sda scl p3 p2 p1 p0 adc 2.2 nf 10 nf 1 nf 1 nf 3.9 k w 2.7 k w 5 v 33 v 27 k w 18 pf 1 nf tuning voltage vco output vco micro- controller 47 nf 4 mhz loop bandwidth most of the applications the TSA5059 are dedicated for require a large loop bandwidth, in the order of a few khz to a few tens of khz. the calculation of the loop filter elements has to be done for each application, while it depends on the vco slope and phase noise, as well as the reference frequency and charge pump current. a simulation of the loop can easily be done by using the simpata software from philips. reference source the TSA5059 is well suited to be used with a 4 mhz crystal connected to pin xtal. philips crystal ordering code 4322 143 04093 is recommended in this case. it is however possible to use a crystal with an higher frequency (up to 16 mhz) to improve the noise performance. when choosing a crystal, one should take notice to select a crystal able to withstand the drive level of the TSA5059 without suffering from accelerated ageing. it is also possible to feed pin xtal with an external signal between 2 and 20 mhz, coming from an external oscillator or from the pin xt/comp of another TSA5059, when more than one synthesizer is present in the same application. then the application given in fig.5 should be used. if the signal at pin xt/comp is not used in an application, the output should be switched off (xce = 0, xcs = 0). this pin should then be open.
1999 oct 05 16 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 handbook, full pagewidth TSA5059 fce124 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1.2 k w 18 pf 4 mhz TSA5059 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1.0 nf fig.5 application for using one crystal with two TSA5059s. i 2 c-bus crosstalk and loop ampli?er the TSA5059 includes a loop amplifier between pin cp and pin vt. while this amplifier shares the same ground pin as the i 2 c-bus, there may be some i 2 c-bus crosstalk. the best way to avoid any i 2 c-bus crosstalk, both in the pll ic and in the application (i.e. parasitic coupling between the i 2 c-bus lines and the vco coil), is to avoid the i 2 c-bus signal to come in the rf part by using an i 2 c-bus gate that allows only the messages for the pll to go to the pll, and to avoid unnecessary repeated sending. such a gate is integrated in most of the philips digital demodulators. if i 2 c-bus crosstalk is still a problem, it is possible not to use the internal amplifier, and to replace it with a nmos transistor in the application as given in fig.6. in this case the pin vt is left open, and it is possible to implement on the pcb the foot print for a jumper between the tuning voltage line and pin vt to be able to choose either the internal amplifier (mounting the jumper and not the nmos transistor) or the external amplifier (mounting the nmos transistor and not the jumper). it is recommended to use a bsh111 or bsh121 n-channel mos transistor. the threshold voltage of the transistor has to be lower than 2.0 v.
1999 oct 05 17 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 fig.6 application for using an external loop amplifier. handbook, full pagewidth fce417 vco 1 16 cp vt 33 v 27 k w 2.7 k w 1 nf 2.7 pf 3.9 k w 2.2 nf 47 nf bsh111 or bsh121 jumper (optional) tuning voltage rf input impedance fig.7 rf input impedance. handbook, full pagewidth 0.2 0.5 1 2 5 10 0.2 0.5 1 2 5 10 0 + j - j fce418 0.5 1 0.2 10 5 2 64mhz 2.7ghz
1999 oct 05 18 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 package outlines x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 95-01-23 97-05-22 076e07s ms-012ac 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
1999 oct 05 19 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.00 1.4 1.2 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 1.0 sot369-1 94-04-20 95-02-04 w m q a a 1 a 2 b p d y h e l p q detail x e z e c l v m a x (a ) 3 a 0.25 18 16 9 pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 4.4 mm sot369-1 a max. 1.5
1999 oct 05 20 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 oct 05 21 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 oct 05 22 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 oct 05 23 philips semiconductors preliminary speci?cation 2.7 ghz i 2 c-bus controlled low phase noise frequency synthesizer TSA5059 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 68 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 545004/01/pp 24 date of release: 1999 oct 05 document order number: 9397 750 05435

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